EDN

Applying Constrained-Random Verification to Microprocessors

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...
Design-Reuse

Using Vera and Constrained-Random Verification to Improve DesignWare Core Quality

As more system-on-chip (SoC) engineers rely on re-use to cut design time and reduce risk, the demand for synthesizable cores and other forms of intellectual property (IP) continues to rise ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification

UVM testbenches for blocks are adequate until the stage of a subsystem with one or more processors. The new generation of constrained-random test cases based on scenario models can take it from there.
Design-Reuse

Methodology Independent Exhaustive Constraint Solver for Random Verification and Regression Generation

Abstract — Constrained random verification is a standard industry approach to test digital intellectual properties. Currently used randomization methods do not guarantee unique testcase with different ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification (.PDF download)

Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench ...