Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low. Fig 2. When a CMOS input pin is at logic high or low ...

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...